I have been working on SAR ADC design for the past couple of years and although it is a straightforward Nyquist ADC but it has a lot of issues that need greater understanding and discussion.
Some of the major aspects of SAR ADC that have always bothered me are
- Is matching of capacitors or the layout of the capacitors , the limitation for linearity of the capacitive DAC array in a SAR ADC?
- Is having a fully binary Capacitive DAC SAR better than a split-cap or a BWA (binary weighted with attenuation) DAC keeping in mind the previous question ?
- Is top-plate sampling better than bottom-plate sampling or vice-versa ?
- How is SAR ADC an energy efficient ADC when it needs a large input buffer and a reference voltage buffer to drive it at medium to high speeds and medium resolutions?
I know there are many other questions and if you just think at the top-level it seems that it is not the best choice but still it is dominating the academia for quite some time and continues to do so.
Me and my colleagues were discussing how can we improve the speed of “spectre” simulations in Cadence especially when we want to run post parasitics extracted simulations. I have been using ADE-XL for the past year and definitely it is a very nice upgrade to have from ADE-L (but it takes up a lot of licenses using the Cadence token system). So in ADE-XL there is an option of multiprocessing but is limited to simulating different corners of the same circuit simultaneously. Remember that just defining the maximum number of processors is not the best choice, you are going to slow down your computer from operating anything in the background even the Linux operating system. Anyways, I am pretty sure from my experience that Cadence ADE-XL does not accelerates the solution of one single circuit for a single corner. So do we have any other option? As we discussed, we came to the conclusion that the multi-processing ability does not appear in ADE-L for “spectre”. It does appear for “ultrasim” simulator which is supposedly partitioning the circuits based on analog and digital signals. Similarly another simulator known as “aps” (marketed as Cadence spectre Accelerated Parallel Simulator) which is relatively a recent product, has substantial improvement over “spectre“. Still whenever in mixed-signal circuits the clock limited blocks are the biggest source of slowing down the overall simulations and it is just impossible to do post parastics extracted simulation for such large chips.
I presented a seminar on current trends in digitally assisted RF circuits which because of limited time wasn’t very deep in its discourse but it does give an overview of how people are contributing to this area. This presentation on digitally Assisted RF Circuits is available in pdf format here so that anyone can build up on it later.
Here is my MS thesis defense presentation and proposal. Although I feel that I had a lot of things to improve especially in my design methodology and novelty of the design. Nevertheless I learned a lot from this experience and hope to build on it. It will be a good reference for people who are just getting into the area of circuit design of a Continous-Time (CT) Delta-Sigma Modulator. You can see and download the presentation from here.
In addition I would recommend some literature and modeling issues to review before you enter this topic of research
- Tutorial and Survey of Delta-Sigma Modulators by De La Rosa [Paper].
- Understanding Delta-Sigma Modulators by Richard Schreier [Book].
- Matlab Del-Sig toolbox by Richard Schreier. [Matlab system modeling of DSM]
- Matlab SD toolbox by Simon Brigati. [Signal level modeling and non-idealities, really useful for determining the block characteristics like Opamp/OTA gain, feedback gain etc]. This paper titled “Improved Modeling of Sigma-Delta Modulator
Non-Idealities in SIMULINK”- which is related to this toolbox will explain its application in detail.